Scalable Floating-Point Matrix Inversion Design Using Vivado High-Level Synthesis (XAPP1317)

Matrix inversion is widely used in numerous signal processing and data analysis algorithms. Many of these algorithms use a floating-point data format to accommodate large dynamic ranges of the random matrices (see Adaptive Beamforming for Radar: Floating-Point QRD+WBS in an FPGA (WP452) [Ref 1]). This application note focuses on the design of a scalable matrix inversion function using the Vivado® High-Level Synthesis (HLS) tool, which takes the source code in C programming language and generates highly efficient synthesizable Verilog or VHDL code for the FPGA. The size of the matrix is defined in the C header file and can be easily changed. The example design employs a pipelined architecture to achieve high throughput for per-user based massive multiple-input, multiple-output (MIMO) wireless communication systems.